Please use this identifier to cite or link to this item: http://essuir.sumdu.edu.ua/handle/123456789/35651
Title: A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness
Authors: Jana, Biswabandhu
Jana, Anindya
Sing, Jamuna Kanta
Sarkar, Subir Kumar
Keywords: Single electron transistor (SET)
CMOS
Hybrid CMOS-SET circuits
MIB
Noise margin (NM)
T-Spice
Issue Year: 2013
Publisher: Sumy State University
Citation: A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness [Текст] / B. Jana, A. Jana, J.K. Sing, S.K. Sarkar // Журнал нано- та електронної фізики. - 2013. - Т.5, №3, Ч.ІІ. - 03057.
Abstract: The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift register to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35651
URI: http://essuir.sumdu.edu.ua/handle/123456789/35651
Type: Article
Appears in Collections:Журнал нано- та електронної фізики (Journal of nano- and electronic physics)

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